1. Field of the Invention
The present invention relates to a high speed digital computer adapted for vector processing, and more particularly, to a vector data processing system in which indirect address instructions can be carried out.
2. Description of the Prior Art
Recently, to provide more rapid processing, vector computers have been developed. In one example of the prior art, the vector computer comprises a plurality of vector registers, and a plurality of pipelines such as access pipelines, an add operation pipeline, a multiply operation pipeline, a division operation pipeline, and a mask pipeline. In such a vector computer, data of a main storage unit is loaded via one of the access pipelines in the vector registers, and vector operation is carried out by supplying two operand vectors to one of the operation pipelines to obtain a result vector, which is again written into the vector registers. Then, the final result vector is stored from the vector registers via one of the access pipelines in the main storage unit, thereby completing one data processing sequence. That is, the access pipelines are used for carrying out load instructions and store instructions.
There are two kinds of load/store instructions, i.e., direct address load/store instructions and indirect address load/store instructions. Here, in a direct address load/store instruction mode, addresses are supplied from a vector instruction control circuit directly to the access pipelines, while in an indirect address load/store instruction mode, addresses are supplied by the vector instruction control circuit from the vector registers to the access pipelines.
When carrying out a direct address load instruction for transmitting data from the main storage unit to the vector registers, only one access is necessary for the vector registers, and therefore, only one write bus is necessary for each access pipeline. Similarly, when carrying out a direct address store instruction for transmitting data from the vector registers to the main storage unit, only one access is necessary for the vector registers, and therefore, only one read bus is necessary for each access pipeline. Thus, one write bus and one read bus are necessary for each access pipeline to perform direct address instructions.
When carrying out an indirect address load instruction for transmitting data from the main storage unit to the vector registers, two accesses, i.e., one access for generating an indirect address and one access for loading data in the vector registers, are necessary for the vector registers, and therefore, one read bus and one write bus are necessary for each access pipeline. Similary, when carrying out an indirect address store instruction for transmitting data from the vector registers to the main storage unit, two accesses, i.e., one access for generating an indirect address and one access for storing data in the main storage unit, are necessary for the vector registers, and therefore, two read buses are necessary for each access pipeline. Thus, two read buses and one write bus are necessary for each access pipeline to perform indirect address instructions.
Thus, to perform indirect address load/store instructions, one additional read bus is necessary for each access pipeline, and therefore, two additional read buses are necessary for the two access pipelines. Obviously an increased number of access pipelines will require additional read buses. Such additional read buses make necessary an increase of the multiplexity of interleaves of the vector registers, thereby increasing the manufacturing cost of the vector computer.